1. Field
One embodiment of the invention relates to an amplitude shift keying (ASK) demodulator.
2. Description of the Related Art
An ASK demodulator circuit for demodulating an ASK-modulated input signal generally comprises a rectifier circuit and a comparator. The rectifier circuit rectifies and detects a signal received with an antenna, and produces a demodulated signal. This demodulated signal is compared with a threshold by a comparator, amplified to a logical level and thereby converted to a binary signal. The comparator is often provided with a hysteresis function to suppress an error resulting from noise. With the hysteresis function, the comparator becomes resistant to the noise; however, it is difficult to improve receiver sensitivity of the comparator.
In general, receiver sensitivity of a rectifier circuit is low since the rectifier circuit can not rectify input signal power smaller than a threshold of a diode (about 0.7V). A high-gain rectifier circuit disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2006-34085 comprises an NMOS transistor, and the threshold voltage is caused to substantially be 0V by applying a voltage corresponding to a threshold voltage of the NMOS transistor between a gate and a source. This configuration of the high-gain rectifier circuit enables to rectify even a minute AC signal having an effective value equal to or less than the threshold. That is, according to the high-gain rectifier circuit, receiver sensitivity can be improved.
In order to improve receiver sensitivity of a comparator, it is necessary to set a threshold low while eliminating hysteresis. In such a case, a DC offset voltage due to variations in an element contained in the comparator needs to be taken into consideration. When the DC offset voltage largely varies in the positive-value side, the receiver sensitivity may decrease. When the DC offset voltage largely varies in the negative-value side, a logical level of an output may be “1” even if an input voltage is 0V (erroneous operation). To prevent the error, the threshold of the comparator should be set high in consideration of the variation in the DC offset voltage. Therefore, it is difficult to improve receiver sensitivity of the comparator. Furthermore, a size of an element needs to be larger to reduce the DC offset voltage due to variation in the element; thus, the cost will be increased.
According to the high-gain rectifier circuit disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2006-34085, bias voltage is supplied to the rectifier circuit using a clock signal. Therefore, a noise appears in an output of the rectifier circuit in synchronization with the clock signal. To suppress the noise that is synchronized with the clock signal, a time constant of the rectifier circuit output needs to be larger, and it becomes therefore difficult to improve a data rate.